Thin film devices, such as micro-electromechanical systems (MEMS) and thin film capacitors, typically require an atomically smooth surface for high yield manufacturing. These thin film devices are generally made from layers deposited and patterned in a series of successive steps, one layer at a time, that build up the final device structure. The topography created on the surface by underlying patterned films, such as polysilicon, can cause significant problems for the subsequent formation and patterning of layers, such as stringers, striations in spin-on films and focus problems in photolithography. Previous efforts to reduce these and other problems associated with depositing thin film layers on top of a patterned polysilicon have included limiting the thickness of the polysilicon layer, typically to 1 um. It would be advantageous to provide an extremely planar surface on a patterned polysilicon layer in order to reduce or eliminate the problems associated with forming layers on top of patterned films.
In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portion of the polysilicon film for a first amount of time to define a pattern in the masked portion of the polysilicon film; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that is coplanar with the patterned polysilicon film; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon film have about the same thickness and form a planar surface.
A thin film capacitor having an integrated polysilicon decoupling resistor may include a substrate, a patterned polysilicon layer and a thin film capacitor. The patterned polysilicon layer may be fabricated on the substrate to form the integrated polysilicon decoupling resistor, the patterned polysilicon layer having a planar surface. The thin film capacitor may be fabricated on the planar surface of the patterned polysilicon layer. The patterned polysilicon layer may be fabricated by etching masked portions of a deposited polysilicon film for a first amount of time to define a pattern in the polysilicon film, and oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that is coplanar with the patterned polysilicon film, the first and second amounts of time being selected such that the oxide layer and the patterned polysilicon film have about the same thickness and form the planar surface.
A MEMS beam resonator may include a substrate, a first patterned polysilicon layer, and a second patterned polysilicon layer. The first patterned polysilicon layer may be fabricated on the substrate and may have a planar surface. The second patterned polysilicon layer may be spaced from the first patterned polysilicon layer by a small gap, wherein the small gap is fabricated using a sacrificial oxide that is formed on the planar surface of the first patterned polysilicon layer. The first patterned polysilicon layer may be fabricated by etching masked portions of a deposited polysilicon film for a first amount of time to define a pattern in the polysilicon film, and oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that is coplanar with the patterned polysilicon film, the first and second amounts of time being selected such that the oxide layer and the patterned polysilicon film have about the same thickness and form the planar surface.